1. Field of the Invention
The present invention relates to a semiconductor device, more specifically to a computer implemented method for designing a semiconductor device which includes diagonal wires connected with a plurality of vias, and an automated design system and a semiconductor device designed by the computer implemented method.
2. Description of the Related Art
With the increased miniaturization of an integrated circuit, in a process of designing masks, it has become difficult to manufacture desined wires and vias. Therefore, various methodologies have been developed to manufacture the wires and the vias delineated on the masks as designed to achieve high manufacturing yield and reliability of the integrated circuit.
With regard to interconnect wires of the integrated circuit, a plurality of vias (hereinafter, referred to as “double cut via”) has been provided to connect with upper and lower wire layers to prevent an increase in resistance caused by defective vias, and decreased yield caused by disconnection of wires. In addition, to prevent incomplete interconnection between the vias and the wires, end portions of the wires can be extended or expanded by use of optical proximity correction (OPC) or the like.
Recently, to reduce higher resistance between wires, a “diagonal routing” technique has been used in addition to the traditional “right-angle routing” technique which orients wires to 0 or 90 degrees. Since the diagonal routing technique orients wires to 45 or 135 degrees, transistors and cells are routed in a shortest distance.
However, when replacing via with the double cut via, there is a case that widths of the line patterns do not become uniform. Therefore, it has become difficult to manufacture the line patterns and the manufacturing yield and reliability may be decreased. Further, it is necessary to avoid the occurrence of design violation such as patterns having acute angles when replacing the via with the double cut via.